The present disclosure relates to a semiconductor integrated circuit device including a core region and an I/O region.
In recent years, semiconductor integrated circuits have further increased their scale to have an increasing number of input and output signals. Therefore, arranging input/output cells (I/O cells) in a single row to surround a core region may define the area of the semiconductor integrated circuit, thus increasing the area of a device including the semiconductor integrated circuit, i.e., a semiconductor integrated circuit device, which is not beneficial.
Japanese Unexamined Patent Publication No. 2000-21987 discloses a configuration for a semiconductor integrated circuit in which I/O cells are arranged in multiple rows in a peripheral portion of the circuit, thereby preventing the I/O cells from defining the area of the semiconductor integrated circuit.